Universal Verification Methodology (UVM) is a method of verifying digital designs (FPGA design in our case) and is developed in the SystemVerilog (SV) coding language. UVM comes with a whole host of reusable standardised components which are very useful for building testbenches and verifying systems architecture. However, to move from standard VHDL testbench verification to SV/UVM verification requires some training and hands-on experience. There are a number of our clients who ask for this skillset so it makes sense for Covnetics to look at training up engineers and increasing our expertise in this area. We use Doulos for all our development training needs, so we’ve put Nick, one of our senior engineers with over 30 years of FPGA (and ASIC) experience using VHDL, through the Doulos SV/UVM course. Nick said this about the course, “Undertaking the SV/UVM course was interesting and quite different from the VHDL testbenches I’ve developed in the past. With my software experience the transition to a different verification methodology was slightly easier. I’m looking forward to putting my new skills into practice.” Nick has just started to support a customer where hopefully he can use some of his new skills in the verification testbench development. Ram Dey, managing director at Covnetics, said this, “We realise that our customers have different requirements and to support that we need to keep our engineers trained up in different methods and practices. As an FPGA consultancy we need to provide the right services which our customers require to help them move their own project developments forward and SV/UVM is one of those services. Nick is just the first engineer who has undertaken the training and will be supporting customers in this area the future. We will be training other engineers going forward.”
SV/UVM training – do we need it ?
